Revolutionizing CMOS Sensors with Smart ADC #sciencefather #researcher #cmos

 

📸 Smarter, Quieter, and More Efficient: Interval-Adaptive CMS ADC for CMOS Image Sensors

In the world of CMOS Image Sensors (CIS), achieving crystal-clear images often comes down to one big challenge — reducing readout noise 🎯. Correlated Multiple Sampling (CMS) has long been the go-to method for this, but it comes with a trade-off: longer conversion times ⏳ and higher power consumption ⚡ in the ADC.

This research introduces a game-changing solution — an Interval-Adaptive Correlated Multiple Sampling ADC with Prejudgment Logic 🤖. Here’s how it works:

1️⃣ Two-Step Smart Conversion

• Step 1: A 6-bit SAR ADC does a coarse conversion to quickly select a small-range interval.

• Step 2: Another 6-bit fine conversion is performed only in that interval for higher accuracy.

2️⃣ Power-Saving Prejudgment Logic

• By recognizing that neighboring pixels often have similar values 🖼️, the system can skip the coarse step entirely in many cases.

• The trick? Two columns share one SAR ADC, making this possible without extra hardware overhead.

🛠 Fabrication & Performance

• Process: 130 nm CIS

• DNL: –0.75 / +1 LSB 📏

• INL: –1.2 / +0.5 LSB 📐

• Input-Referred Noise: 122.5 µVrms 🔇

• Conversion Time: Faster in bright conditions ☀️, adaptive in dark conditions 🌙

• Power Savings: Up to 20.3% less column power compared to traditional CMS ADC ⚡✅

💡 Why it matters: This approach delivers low-noise imaging, shorter readout times, and significant power savings — making it ideal for high-performance cameras, mobile devices 📱, and machine vision systems 🤖.

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